This invention relates to checking the operation of a sequential logic circuit.
A sequential logic circuit is a circuit with a plurality of distinct internal states and which changes stage in a predetermined manner in response to one or more condition input signals.
It is often desirable to provide some means for checking the operation of such a circuit during its actual operation to ensure that it is operating correctly. One way of doing this would be to duplicate the entire circuit and to compare the states of the duplicated circuits at each stage of operation. Any discrepancy between the duplicated circuits would indicate an error. However, the disadvantage of this method is that it is very expensive in terms of the amount of hardware required.
One object of the present invention is to provide a novel way of checking a sequential logic circuit which does not require duplication of the circuit.